Fix endianess of registers

This commit is contained in:
Michael Zanetti 2022-04-06 13:44:04 +02:00
parent b1de77c63d
commit fd78e9b9fe

View File

@ -1,6 +1,6 @@
{
"protocol": "RTU",
"endianness": "BigEndian",
"endianness": "LittleEndian",
"blocks": [
{
"id": "e3",